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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14094B 8-Stage Shift/Store Register with Three-State Outputs
The MC14094B combines an 8-stage shift register with a data latch for each stage and a three-state output from each latch. Data is shifted on the positive clock transition and is shifted from the seventh stage to two serial outputs. The QS output data is for use in high-speed cascaded systems. The QS output data is shifted on the following negative clock transition for use in low-speed cascaded systems. Data from each stage of the shift register is latched on the negative transition of the strobe input. Data propagates through the latch while strobe is high. Outputs of the eight data latches are controlled by three-state buffers which are placed in the high-impedance state by a logic Low on Output Enable. * Three-State Outputs * Capable of Driving Two Low-Power TTL Loads or One Low-Power Schottky TTL Load Over the Rated Temperature Range * Input Diode Protection * Data Latch * Dual Outputs for Data Out on Both Positive and Negative Clock Transitions * Useful for Serial-to-Parallel Data Conversion * Pin-for-Pin Compatible with CD4094B MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol VDD Parameter DC Supply Voltage MC14XXXBCP MC14XXXBCL MC14XXXBD L SUFFIX CERAMIC CASE 620
P SUFFIX PLASTIC CASE 648
D SUFFIX SOIC CASE 751B
ORDERING INFORMATION
Plastic Ceramic SOIC
TA = - 55 to 125C for all packages.
IIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I III IIIIIIII I I I I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I I I I I IIIIIIIIIIIIIIIIIIIII I I III I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII
Value Unit V V - 0.5 to + 18.0 10 500 Vin, Vout Iin, Iout PD TL Input or Output Voltage (DC or Transient) - 0.5 to VDD + 0.5 Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature mA mW Tstg - 65 to + 150 260
PIN ASSIGNMENT
STROBE DATA CLOCK Q1 Q2 Q3 Q4 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD OUTPUT ENABLE Q5 Q6 Q7 Q8 QS QS
_C _C
Lead Temperature (8-Second Soldering)
* Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C Output Enable 0 0 1 1 1 1 Parallel Outputs Strobe X X 0 1 1 1 Data X X X 0 1 1 Q1 Z Z No Chg. 0 1 No Chg. QN Z Z No Chg. QN-1 QN-1 No Chg. Serial Outputs QS* Q7 No Chg. Q7 Q7 Q7 No Chg. QS No Chg. Q7 No Chg. No Chg. No Chg. Q7
Clock
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
v
v
Z = High Impedance X = Don't Care * At the positive clock edge, information in the 7th shift register stage is transferred to Q8 and QS.
REV 3 1/94
(c)MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995
MC14094B 1
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I III I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I I IIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I I I III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I I I I II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I I II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III IIII I III IIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIII IIIIII IIII I I I II II II III I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
** The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.001.
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
3-State Output Leakage Current
Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching)
Quiescent Current (Per Package)
Input Capacitance (Vin = 0)
Input Current
Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc)
Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)
Output Voltage Vin = VDD or 0
MC14094B 2
(VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Vin = 0 or VDD (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Characteristic "1" Level "1" Level "0" Level Source Sink Symbol VOH VOL IOH IDD VIH IOL Cin VIL ITL Iin IT VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 15 15 -- - 3.0 - 0.64 - 1.6 - 4.2 4.95 9.95 14.95 0.64 1.6 4.2 Min 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- -- -- - 55_C 0.1 0.1 0.05 0.05 0.05 Max 5.0 10 20 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- - 2.4 - 0.51 - 1.3 - 3.4 4.95 9.95 14.95 0.51 1.3 3.4 Min 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- -- -- 0.00001 0.0001 - 4.2 - 0.88 - 2.25 - 8.8 Typ # 0.005 0.010 0.015 25_C 0.88 2.25 8.8 2.75 5.50 8.25 2.25 4.50 6.75 5.0 5.0 10 15 0 0 0
IT = (4.1 A/kHz) f + IDD IT = (14 A/kHz) f + IDD IT = (140 A/kHz) f + IDD
MOTOROLA CMOS LOGIC DATA
0.1 0.1 0.05 0.05 0.05 Max 5.0 10 20 7.5 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- - 1.7 - 0.36 - 0.9 - 2.4 4.95 9.95 14.95 0.36 0.9 2.4 Min 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- -- -- 125_C 3.0 1.0 0.05 0.05 0.05 Max 150 300 600 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- mAdc mAdc Adc Adc Adc Unit Vdc Vdc Vdc Vdc A pF
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II III I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II III I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II III I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II III I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II III I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II III I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II III I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII III II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
* The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Strobe Pulse Width
Clock Pulse Frequency
Clock Rise and Fall Time
Clock Pulse Width, High
Hold Time Clock to Data
Setup Time Data in to Clock
Output Rise and Fall Time tTLH, tTHL = (1.35 ns/pF) CL + 33 ns tTLH, tTHL = (0.6 ns/pF) CL + 20 ns tTLH, tTHL = (0.4 ns/pF) CL + 20 ns Propagation Delay Time Clock to Serial out QS tPLH, tPHL = (0.90 ns/pF) CL + 305 ns tPLH, tPHL = (0.36 ns/pF) CL + 107 ns tPLH, tPHL = (0.26 ns/pF) C L + 82 ns
MOTOROLA CMOS LOGIC DATA
Output Enable to Output tPHZ, tPZL = (0.90 ns/pF) CL + 95 ns tPHZ, tPZL = (0.36 ns/PF) CL + 57 ns tPHZ, tPZL = (0.26 ns/pF) CL + 42 ns tPLZ, tPZH = (0.90 ns/pF) CL + 180 ns tPLZ, tPZH = (0.36 ns/pF) CL + 77 ns tPLZ, tPZH = (0.26 ns/pF) CL + 57 ns Strobe to Parallel out tPLH, tPHL = (0.90 ns/pF) CL + 245 ns tPLH, tPHL = (0.36 ns/pF) C L + 127 ns tPLH, tPHL = (0.26 ns/pF) CL + 87 ns Clock to Parallel out tPLH, tPHL = (0.90 ns/pF) CL + 375 ns tPLH, tPHL = (0.35 ns/pF) CL + 177 ns tPLH, tPHL = (0.26 ns/pF) CL + 122 ns Clock to Serial out Q'S tPLH, tPHL = (0.90 ns/pF) CL + 350 ns tPLH, tPHL = (0.36 ns/pF) CL + 149 ns tPLH, tPHL = (0.26 ns/pF) CL + 62 ns Characteristic CLOCK DATA O.E. ST FOR tPHZ AND tPZH VSS
3-STATE TEST CIRCUIT
Symbol
tPHZ, tPZL
tPLH, tPHL
tTLH, tTHL
tPLZ, tPZH
tr(cl) tf(cl)
tWH
tWL
tsu
fcl
th
1k
50 pF
FOR tPLZ AND tPZL VDD
VDD Vdc
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5 10 15
OUTPUT
Min
200 80 70
200 100 83
125 55 35
0 20 20
-- -- --
-- -- --
-- -- --
-- -- --
-- -- --
-- -- --
-- -- --
-- -- --
-- -- --
Typ #
- 40 - 10 0
100 40 35
100 50 40
225 95 70
140 75 55
290 145 100
420 195 135
230 110 75
350 125 95
100 50 40
2.5 5.0 6.0
60 30 20
-- -- --
1.25 2.5 3.0
Max
450 190 140
280 150 110
580 290 200
840 390 270
460 220 150
600 250 190
200 100 80
15 5.0 4.0
-- -- --
-- -- --
-- -- --
-- -- --
MC14094B 3
MHz Unit s ns ns ns ns ns ns
BLOCK DIAGRAM
REGISTER STAGE 1 CLOCK 2 CLOCK LATCH 1 STROBE 3-STATE BUFFER 1 VDD
*
SERIAL DATA IN CLOCK CLOCK STROBE STROBE 4 Q1
CLOCK 15
CLOCK
STROBE
*
2 OUTPUT ENABLE 3 4 5 6 7 REGISTER STAGE 2 REGISTER STAGE 3 REGISTER STAGE 4 REGISTER STAGE 5 REGISTER STAGE 6 REGISTER STAGE 7 LATCH 2 LATCH 3 LATCH 4 LATCH 5 LATCH 6 LATCH 7 3-STATE BUFFER 2 3-STATE BUFFER 3 3-STATE BUFFER 4 3-STATE BUFFER 5 3-STATE BUFFER 6 3-STATE BUFFER 7 5 6 7 14 13 12 Q2 Q3 Q4 Q5 Q6 Q7
8
REGISTER STAGE 8 CLOCK CLOCK
LATCH 8 STROBE STROBE CLOCK
3-STATE BUFFER 8
11
Q8
10 3
QS
*
CLOCK
CLOCK CLOCK
CLOCK
CLOCK
1
*
STROBE
STROBE STROBE
*Input Protection Diodes
CLOCK 9 QS
DYNAMIC TIMING DIAGRAM
tWH tr 50% th 50% 90% 10% tsu
2
tf
3
CLOCK
DATA IN tWL
1
STROBE
15
OUTPUT ENABLE tPLH
50% tPHL 90% 10% tTHL tPLH 50% tPLH tPLH tPHZ 90% 10% tPHL 50% tPZH tPLZ
50% tPZL 90% 10%
N
Q1
Q7
tTLH
90% 10%
9
QS
tPHL 50%
10 QS
50%
MC14094B 4
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE V
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01
-B-
1 8
C
L
-T-
SEATING PLANE
N E F D G
16 PL
K M J
16 PL
0.25 (0.010)
M
M
TB
S
0.25 (0.010)
TA
S
P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
MOTOROLA CMOS LOGIC DATA
MC14094B 5
OUTLINE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
-A-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
16
9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
DIM A B C D F G J K M P R
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MC14094B 6
*MC14094B/D*
MOTOROLA CMOS LOGIC DATA MC14094B/D

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